1. Field of the Invention
The instant disclosure relates to a static random access memory cell; in particular, to a non-volatile static random access memory using a 7T1R cell with initialization and pulse overwrite.
2. Description of Related Art
In order to reduce required power consumption, minimizing the size of the integrated circuit memory devices in semiconductors is still the direction to strive for. Memory devices in semiconductors include static random access memory (SRAM) and dynamic random access memory (DRAM). A DRAM memory cell only has one transistor and a capacitor, which provides high integrability. However, since DRAM required refresh operation, high power consumption and slow speed makes DRAM a memory choice limited to mostly computer memories. On the other hand, SRAM cell has bistability, which means with the appropriate power, SRAM can continuously maintain the original state. SRAM can operate in high speed under low power consumption, such that computers mostly use a lot of cache SRAM. Other applications include embedded memory, and network device memory.
Conventional structures of common SRAM cells include six transistors (6T). Please refer to FIG. 1 as a circuit diagram of a conventional 6T static random access memory cell. The conventional 6T static random access memory cell 1 includes a first inverter 11, a second inverter 12, a first access transistor M5, and a second access transistor M6. The first inverter 11 includes a first pull-up transistor M1 and a first pull-down transistor M3, whereas the second inverter 12 includes a second pull-up transistor M2 and a second pull-down transistor M4. The first pull-up transistor M1 has a source terminal and the second pull-up transistor M2 has a source terminal cooperatively coupled to a voltage supply VDD. The first pull-down transistor M3 has a source terminal and the second pull-down transistor M4 has a source terminal cooperatively coupled to a low voltage supply VSS. The first pull-down transistor M3 has a drain terminal and the first pull-up transistor M1 has a drain terminal cooperatively coupled to form a first output node Q of the first inverter 11. The second pull-down transistor M4 has a drain terminal and the second pull-up transistor M2 has a drain terminal cooperatively coupled to form a second output node QB of the second inverter 12.
The first access transistor M5 has a gate terminal coupled to a word line WL, a source terminal coupled to the first output node Q, and a drain terminal coupled to a first bit line BL. The second access transistor M6 has a gate terminal coupled to the word line WL, a source terminal coupled to the second output node QB, and a drain terminal coupled to a second bit line BLB.
Please refer to FIGS. 1 and 2. FIG. 2 is a signal diagram of the conventional 6T static random access memory cell while data are being written thereon. Conventional 6T static random access memory cell 1 must fix the first bit line BL and the second bit line BLB to a group of fixed voltage when data are being written, such that data stored in the first output node Q and the second output node QB are forced to flip.
Please refer to FIGS. 1 and 3. FIG. 3 is a signal diagram of the conventional 6T static random access memory cell while data are being read therefrom. Conventional 6T static random access memory cell 1 must pull the electric potential of word line WL to “1” (refer to the T3-T4 interval as shown in FIG. 3) when data is being read, which is different from writing, the electric potential of the first bit line BL must pull up and be equal to the second bit line BLB before the electric potential of the word line WL pulls up to “1”, and the first bit line BL and the second bit line BLB must have equal electric potentials such as “1” as shown in FIG. 3. When the first bit line BL is equal to the second bit line BLB and floating, the word line WL then provides on signals. The conventional 6T static random access memory cell uses the storage values of the first output node Q and the second output node QB and, via the first access transistor M5 and the second access transistor M6, generates charge sharing and voltage division respectively with the first bit line BL and the second bit line BLB, such that difference in electric potential is induced between the first bit line BL and the second bit line BLB. As shown in FIG. 3, the electric potential signal of the first bit line BL is affected, thus voltage is reduced. Successively, an external signal amplifier (not shown in the figures) amplifies differences in signals and reads out the voltage value as “0” or “1”.
Furthermore, non-volatile SRAM stores data in a non-volatile element. The stored data still remains when the power supply is turned off. Usually, the non-volatile element can be a resistive storage device, such as phase change material (PCM), magnetic tunnel junction (MTJ), or memristor etc. which have been utilized in the phase change random-access memory (PCRAM), the resistive random-access memory (RRAM) or the magnetoresistive random-access memory (MRAM). Then non-volatile SRAM can completely eliminate SRAM leakage during standby.